THALIOX Development

Top-down and staged. Every milestone is independently usable, demonstrable, and falsifies the next stage.

thaliox-os Docs

Milestones

H1 software → H2 specialization → H3 co-designed silicon.

Single-node MVP

Shipped

Rust daemon + LLM + vector memory + autonomous tool-calling + capability gating + gateway. Shipped as v0.1.0.

microVM-ization

Shipped

One-command deploy + snapshot/restore + self-update rollback. The agent now runs inside a real Firecracker microVM — vsock deploy, VM snapshot/restore — atop the software layer. Shipped.

Multi-instance HA

Shipped

Live migration + per-field CRDT merge + a self-healing supervisor (heartbeat → self-heal → reconcile). Shipped.

Cluster + multi-client

Shipped

A fabric carrying VectorMessages between agents and across nodes. Cross-host live migration validated on two KVM machines — process- and microVM-level (the full {VM, host-process} matrix). Teams in four paradigms (Pipeline / Hierarchy / Market / Swarm). The gateway generalized into the cluster front door — capability admission, SSE streaming, peer routing. Shipped.

Learning control plane

Planned

RL scheduling + a supervisor agent + self-optimization — "AI manages AI". Next up.

Pushing down the stack

Planned

eBPF → unikernel / abstract-machine contract → kernel-bypass vector transport → FPGA primitives.

First primitive in silicon

Planned

Tape out a single primitive that is uniquely THALIOX — a MELD silicon primitive (dataflow / capability-memory / vector-transport).

Vertically integrated node

Planned

A complete THALIOX machine — running the self-designed MELD cognitive substrate on co-designed silicon.

Model architecture

A parallel lane: the mind THALIOX runs, chosen by what the OS can snapshot, migrate, gate, and merge — not by benchmark.

WorkhorseRFC-0002 · Accepted

Bounded-State Hybrid + MoE

Fixed-size, serializable runtime state (an agent is snapshottable/migratable), MoE capacity, adaptive compute as the attention-budget knob. Model-State Contract shipped in M2.

Self-designedRFC-0003 · Exploratory

MELD cognitive substrate

Mergeable · Energy-based · Latent · Dataflow. State-as-process, mergeable cognition (the M3 merge primitive), capability-addressed memory. Pillar gates E1–E4 passed at toy scale.

IntegratedRFC-0003 §7

Model on co-designed silicon

MELD's dataflow / capability-memory / vector-transport primitives realized in hardware — the model and the machine co-designed to one TAM contract. Lands in M8.

Entry points

Main repo — thaliox-os

The THALIOX core, rebuilt from scratch in Rust.

TAM Abstract Machine — RFC-0001

Three primitives + five invariants: the shared contract from software to silicon.

Master Plan

The full top-down, staged-moonshot roadmap.

Model architecture — RFC-0002 & RFC-0003

The model THALIOX runs: bounded-state hybrid today, the self-designed MELD substrate next.

Become a contributor

How to contribute and apply for developer access.